1. Field of the Invention
The present invention relates to phase-frequency discriminators and, more particularly, to digital phase-frequency discriminators.
2. Description of the Related Art
A digital phase-frequency discriminator typically provides an output which is related to a phase or frequency relationship between signals input to the discriminator. For example, in a phase lock loop a digital phase-frequency discriminator often is used to compare a reference signal to a signal derived from the output of a voltage controlled oscillator (VCO), to detect the phase or frequency difference between the two signals and to provide an output signal which is related to this difference. The frequency of oscillation of the VCO then can be changed based upon the output signal to decrease this difference. In this manner, the phase or frequency difference between the signals received by the phase-frequency discriminator can be reduced until it becomes substantially zero, indicating that the phase lock loop is substantially in phase lock.
More particulary, a first earlier digital phase-frequency discriminator (DPFD) is labelled with the reference numeral (12) in the exemplary schematic diagram of FIG. 1. The first earlier DPFD (12) comprises respective first and second RS latches (14, 16), each including two cross-coupled NAND gates. The respective first and second RS latches (14, 16) are shown coupled to receive on their respective S input terminals a reference signal and a signal derived from a VCO output signal, and are coupled to provide respective first and second output signals (f.sub.1, f.sub.2). The first earlier DPFD (12) further comprises respective third and fourth RS latches (18, 20), each including two cross-coupled NAND gates. It also includes a reset gate (22) which comprises a four-input NAND gate connected as shown. The reset gate (22) includes an output terminal coupled to the respective R input terminals of the respective first, second, third and fourth RS latches (14, 16, 18, 20).
A second earlier DPFD is labelled with the reference numeral (24) in the exemplary schematic diagram of FIG. 2. The second earlier DPFD (24) comprises respective first and second clocked D flip-flops (26, 28) having their respective clear-Q (CQ) terminals coupled to one another. Respective clock pulse (CP) input terminals of the first and second D flip-flops (26, 28) are shown coupled to a reference signal and to a signal derived from a VCO output signal. The respective D input terminals of the respective first and second D flip-flops (26,28) each have a logical 1 bias signal continuously provided during operation, the respective Q outputs of the respective first and second flip-flops (26, 28) provide respective first and second output signals (f.sub.1, f.sub.2). The respective Q outputs each are fed back into reset gates shown within dashed lines labelled (30) which comprise two NOR gates connected as shown. The reset gates provide a reset signal to the respective clear-Q (CQ) terminals of the respective flip-flops (26, 28).
A third earlier DPFD is labelled with the reference numeral (32) in the exemplary schematic digram of FIG. 3. The third earlier DPFD (32) comprises respective first and second JK flip-flops (34, 36) having their respective clear (C) terminals coupled to one another. Respective clock pulse (CP) input terminals of the first and second JK flip-flops (34, 36) are shown coupled to a reference signal and to a signal derived from a VCO output signal. During operation, respective J input terminals of the respective JK flip-flops (34, 36) are continuously coupled to a logical 1 bias, and respective K input terminals are coupled to electrical ground. The respective Q output terminals provide respective first and second output signals (f.sub.1, f.sub.2). Additionally, the respective Q output terminals are coupled to the input terminals of a reset gate (38) which comprises a NAND logic gate. An output terminal of the NAND logic gate is coupled to the respective clear (C) terminals of the respective first and second JK flip-flops (34, 36).
While these earlier DPFDs generally have been successful, there have been limitations with their use. For example, the first earlier DPFD (12) suffers from crossover distortion near zero phase error. More specifically, the implementation of the first earlier DPFD (12) ordinarily requires a linear predictable relationship between the phase difference between the input signals provided to the DPFD and the respective output signals (f.sub.1, f.sub.2) provided by the DPFD. However, when the input signals provided to the first earlier DPFD (12) are nearly in phase with one another, the reset gate (22) can cause the respective output signals (f.sub.1,f.sub.2) provided by the DPFD (22) to reset before achieving full-logic amplitude levels. Thus, in the region of substantiallY zero phase error, the first earlier DPFD (12) may exhibit crossover distortion which can limit its effectiveness.
The respective second and third DPFDs (24, 32) largely overcome the crossover distortion problem experienced by the first earlier DPFD (12), but they do so at the expense of more complex circuitry. For example, the respective second and third DPFDs (24,32) generally include more gates than the first earlier DPFD (12). In the fabrication of monolithic digital circuits, however, relatively simple circuitry is more desirable because generally it is easier to fabricate, is more reliable and requires less surface area on a semiconductor chip.
Thus, there has been a need for a digital phase-frequency discriminator which substantially does not suffer from crossover distortion near the region of zero phase error and which can be implemented with relatively simple circuitry. The present invention meets this need.